Crypto ASIC blog dedicated fpga bitcoin comparison the intersection of two big passions: a lifetime career in digital system design, and my work since 2013 in cryptocurrency. Most visiting here know me as the lead engineer at dcrASIC, and I’m sure you are excited as I am about our ASIC developments for Decred. A big topic here is news and insight about my work there.
I also hope that you take away from your visits here a greater understanding of ASIC technology. You will find recent articles below, and archived ones in the menu. I’m just getting started with this blog, so check back regularly, or subscribe to keep up with news and posts. If you have questions, feel free to Email me, and I’ll try to address in a post. FAQ: how are full and semi custom ASICs verified? ASIC designs are written in a C-like language called Verilog.
This language allows us to verify our designs by simulation. Verification means that we test our designs before building anything physical. This is critical because ASIC tooling costs are in the millions, and one mistake can mean the tooling will spoiled, costing millions and months of schedule delay. And that could be a fatal mistake.
Verification by simulation and FPGA There are two main levels of logic verification. The first is simulation that runs on a computer, much like VMWare executing a virtual PC. We use a Verilog simulator by Synopsys called VCS, which is really fast as simulators go. However it is really slow compared to the real thing. So we use it during development to test only parts of the chip, or for limited tests of the full chip. The second level of verification is actually implementation on an FPGA, which is essentially a reprogrammable ASIC. We use a 20nm FPGA system by Altera.